Welcome

Welcome to the Intelligent Computing Lab at Yale University! 

We are located in the Electrical & Computer Engineering Department at Dunham Labs. The lab is led by Prof. Priyadarshini Panda. Our lab’s research focuses on developing algorithm and hardware design solutions to enable energy-efficient, sustainable and ubiquitous artificial intelligence (AI) technologies. We are inspired by the brain and embrace the nature’s blueprint of integrating efficiency, robustness and adapatibility together as we shape the future of sustainable AI.

Research Interests:

1. Neuromorphic Computing 

  • Bio-inspired Spiking Neural Networks 
  • Emerging Compute-in-Memory based Hardware Accelerators (Device-Circuit-Architecture-Algorithm Co-Simulation and Optimization)

​2. Efficient Machine Learning 

  • Compression-friendly (sparsity and quantization) algorithm design for Transformers,  LLMs and foundation models  
  • Algorithm-Hardware Co-Design,  System Integration and Acceleration on FPGA, SoC & ASIC

Please check out our Research page and Publications to learn more about our research focus and recent works.

Research Highlights:

  1. Oct. 2024 - When In-memory Computing Meets Spiking Neural Networks – A Perspective on Device-Circuit-System-and-Algorithm Co-design appears in Applied Physics Reviews 2024. This review explores the synergy between Spiking Neural Networks (SNNs) and analog In-Memory Computing (IMC) architectures, emphasizing their potential for low-power edge computing. By investigating the interdependencies between algorithms, devices, and system parameters, we identify key bottlenecks and propose SNN-specific algorithm-hardware co-design techniques to enhance performance in neuromorphic systems. [Paper]

  2. Sept. 2024 - GenQ: Quantization in Low Data Regimes with Generative Synthetic Data appears in ECCV 2024. GenQ uses Generative AI based stable diffusion models to create photorealistic synthetic data for neural network quantization in scenarios with limited or restricted training data. Our method significantly outperforms existing approaches, achieving 76.10% accuracy on ImageNet with a 4-bit QAT-based ResNet-50, surpassing the latest method by 5.4%. [Code, Paper]

  3. Sept. 2024 - One-stage Prompt-based Continual Learning appears in ECCV 2024. We propose a one-stage Prompt-based Continual Learning (PCL) transformer framework that reduces computational costs by ~50% by directly using intermediate layer embeddings as a prompt query. Additionally, our Query-Pool Regularization (QR) loss enhances representation power, achieving state-of-the-art performance on continual learning benchmarks with negligible accuracy loss. [Code, Paper]

  4. Aug. 2024 - LoAS: Fully Temporal-Parallel Dataflow for Dual-Sparse Spiking Neural Networks appears in MICRO 2024. In this work, we introduce a fully temporal-parallel (FTP) dataflow and an FTP-friendly spike compression mechanism to optimize the deployment of dual-sparse SNNs, along with a novel inner join circuit that enhances power and area efficiency without sacrificing throughput. LoAS demonstrates significant speedup (upto 8.5x) and energy reduction (upto 3.8x) compared to prior dual-sparse accelerators. [Code, Paper]

  5. July 2024 - PIVOT- Input-aware Path Selection for Energy-efficient ViT Inference appears in DAC 2024. PIVOT dynamically adjusts the number of attention modules in Vision Transformers (ViT) based on input difficulty to optimize accuracy and throughput. PIVOT reduces the energy-delay product (EDP) by 2.7× with only a 0.2% accuracy drop, when deployed on on Xilinx ZCU104 MPSoC FPGAS. [Paper, Code]