Welcome

Welcome to the Intelligent Computing Lab at Yale University! 

We are located in the Electrical & Computer Engineering Department at Dunham Labs. The lab is led by Prof. Priyadarshini Panda. Our lab’s research focuses on developing algorithm and hardware design solutions to enable energy-efficient, sustainable and ubiquitous artificial intelligence (AI) technologies. We are inspired by the brain and embrace the nature’s blueprint of integrating efficiency, robustness and adapatibility together as we shape the future of sustainable AI.

Research Interests:

1. Neuromorphic Computing 

  • Bio-inspired Spiking Neural Networks 
  • Emerging Compute-in-Memory based Hardware Accelerators (Device-Circuit-Architecture-Algorithm Co-Simulation and Optimization)

​2. Efficient Machine Learning 

  • Compression-friendly (sparsity and quantization) algorithm design for Transformers,  LLMs and foundation models  
  • Algorithm-Hardware Co-Design,  System Integration and Acceleration on FPGA, SoC & ASIC

Please check out our Research page and Publications to learn more about our research focus and recent works.

Research Highlights:

  1. Jan. 2025 - Spiking Transformer with Spatial-Temporal Attention accepted in CVPR 2025. Existing spike-based transformers predominantly focus on spatial attention while neglecting crucial temporal dependencies inherent in spike-based processing. We propose STAtten that introduces a block-wise computation strategy that processes information in spatial temporal chunks, enabling comprehensive feature capture while maintaining the same computational complexity as previous spatial-only approaches. [Code, Paper]

  2. Feb. 2025 - PacQ: A SIMT Microarchitecture for Efficient Dataflow in Hyper-asymmetric GEMMs accepted in DAC 2025. We investigate methods to accelerate GEMM operations involving packed low-precision INT weights and high-precision FP activations. Our approach co-optimizes tile-level packing and dataflow strategies for INT weight matrices. We further design a specialized FP-INT multiplier unit tailored to our packing and dataflow strategies, enabling parallel processing of multiple INT weights. [Paper]

  3. Aug. 2024 - LoAS: Fully Temporal-Parallel Dataflow for Dual-Sparse Spiking Neural Networks appears in MICRO 2024. In this work, we introduce a fully temporal-parallel (FTP) dataflow and an FTP-friendly spike compression mechanism to optimize the deployment of dual-sparse SNNs, along with a novel inner join circuit that enhances power and area efficiency without sacrificing throughput. [Code, Paper]

  4. July 2024 - PIVOT- Input-aware Path Selection for Energy-efficient ViT Inference appears in DAC 2024. PIVOT dynamically adjusts the number of attention modules in Vision Transformers (ViT) based on input difficulty to optimize accuracy and throughput. [Paper, Code]